The present invention is related to a thermal head driving integrated circuit (IC) for entering thereinto a data signal to control energizing of a heating resistive element.
Referring now to FIG. 11, an example of a conventional thermal head driving IC will be briefly explained. Such a thermal head driving integrated circuit is disclosed in, for instance, Japanese Patent Application Laid-Open No. Hei 3-53950. As shown in this drawing, the thermal head driving IC 0 controls energizing of a plurality of heating resistive elements 1, and is equipped with the output terminals DO1 to DO64 connected to the respective heating resistive elements 1. As a result, in this example, the thermal head driving IC 0 can drive 64 of these heating resistive elements 1 at a time. One terminal of the respective heating resistive elements 1 are commonly connected to each other, to which the energizing power supply voltage (for example, 24 V) is applied. The other terminal of the respective hearing resistive elements 1 are connected via the output terminals to drive transistors 2. The drive transistors 2 constitute a driver, and are composed of the N-channel type MOS transistors, in this example. Each of the drive transistors 2 is an open drain output, and all of the sources of these drive transistors 2 are connected to a ground potential VSS. The output terminal of an AND gate circuit 3 is connected to the gate of each drive transistor 2.
Reference numeral 4 shows a shift register for sequentially storing thereinto 1-line data, and is arranged with a series-connection of D-FFs. The shift register 4 is connected via a buffer 8 to a data input terminal SI. Also, the final stage of the shift register 4 is connected via the buffer 8 to a data output terminal SO. In addition, a clock signal is supplied from a control terminal CLK via the buffer 8 to the D-FFs of the respective stages of the shift register 4.
Reference numeral 5 shows a latch circuit for latching the data of the shift register 4 in a batch mode. A latch signal is supplied from a control terminal LCH via the buffer 8. The outputs of the respective stages of the latch circuit 5 are connected to one input terminal of the corresponding AND gate circuit 3. The other input terminals of the respective AND gate circuits 3 are commonly connected to the output terminal of an inverter 7. A strobe signal is applied via a control terminal STB to the input terminal of the inverter 7. It should be noted that the power supply voltage VDD is applied to this thermal head driving IC 0. The input terminal of the inverter 7 is connected via the pull-up resistor to the VDD.
The shift register 4 reads the data signal inputted into the data input terminal SI at the rising edge of the clock signal applied to the control terminal CLK. When the control terminal LCH is at the L-level, the latch circuit 5 latches the data stored in the respective stages of the shift register 4 in the batch mode. When the control terminal LCH is at the H-level, this latch circuit 5 holds the data latched immediately before this control terminal LCH becomes the H level. The data latched in the latch circuit 5 is outputted via the AND gate circuit 3 to the corresponding drive transistor 2 when the control terminal STB is at the L-level.
In other words, when the control terminal STB is at the L-level and the data outputted from the latch circuit 5 is at the H-level, the drive transistor 2 is turned ON, and thus, the corresponding heating resistive element 1 is energized. Conversely, when the control terminal STB is at the L-level and the data is at the L-level, the drive transistor 2 is turned OFF.
When the control terminal STB is set to the H-level, all of the drive transistors 2 are turned OFF irrespective of the output of the latch circuit 5.
For example, when a print operation is carried out on a sheet of paper having a size of A4 in a line sequential manner, 1,728 of the heating resistive elements 1 are arranged in one column. To drive these 1,728 dots of heating resistive elements, 27 of the thermal head driving ICs 0 having 64 driver output terminals need be mounted in one column on a circuit board. In order to reduce the total number of these thermal head driving IC approximately xc2xd, for example, as represented in FIG. 3, such a thermal head driving IC 0 has been developed, in which two stages of shift registers 41 and 42 are built in a series manner. Each of the shift registers 41 and 42 has 64 output stages. As an entire circuit, this IC 0 has 64 2=128 driver output terminals. As a result, the total number of the packaged ICs can be reduced by xc2xd, as compared with that of the ICs indicated in FIG. 11. The front-staged shift register 41 is provided with the data input terminal SI1 and the data output terminal SO1, and also, the rear-staged shift register 2 is equipped with the data input terminal SI2 and the data output terminal SO2.
As a consequence, the operation of the IC itself is similar to that of the IC shown in the drawing. Since both the shift registers 41 and 42 are used in a parallel manner, one set of 64 pieces of data can be written into the respective shift registers 41 and 42 at the same time.
On the other hand, in the IC shown in FIG. 3, when specifically no highspeed printing operation is required, the output terminal SO1 of the front-staged shift register 41 and the input terminal SI2 of the rear-staged shift register 42 are commonly connected to each other by way of a wire bonding and the like, so that both the shift registers 41 and 42 may be used in the series manner. In this case, while the data are entered from the terminal SI1, 128 pieces of such data are sequentially written into the series-connection between the shift register 41 and the shift register 42. In this manner, the total number of input data (namely, the number of input lines of data) with respect to the ICs arranged in one column can be reduced by xc2xd. However, since the intermediate input/output terminals SO1 and SI2 must be connected by way of the wire bonding, there is a demerit in view of cost. Also, since the stray capacitance Cp is produced at the wire bonding portion, it could not avoid such a problem that the data transfer speed between the shift registers 41 and 42 is lowered.
Thus, it is conceivable that a switch circuit is employed which may internally connect/disconnect both the output terminal SO1 of the front-staged shift register 41 and the input terminal SI2 of the rear-staged shift register 42, so that both the shift registers 41 and 42 may be switched in the series use mode and the parallel use mode while preventing an occurrence of a stray capacitance.
In such a case that the series use mode and the parallel use mode are switched by employing such a switch circuit, when the output terminal SO1 and the input terminal SI2 are provided, the total number of input/output pads is increased, so that an IC chip will become bulky and also the total number of bondings will be increased.
However, in the case that both the shift registers 41 and 42 are connected so as to be used in the series manner, both the output terminal SO1 of the front-staged shift register 41 and the input terminal SI2 of the rear-staged shift register 41 and the input terminal SI2 of the rear-staged shift register 42 are used. Also, in the case that both the shift registers 41 and 42 are disconnected from each other so as to be used in the parallel manner, although the input terminal SI2 of the rear-staged shift register 42 is used, the output terminal SO1 of the front-stage shift register 41 is not always used. There is another case that tests are separately carried out as to whether or not both the shift registers 41 and 42 are operated under normal condition. In this case, the output terminal SO1 of the shift register 41 and the input terminal SI2 of the shift register 42 are used. However, both the shift registers 41 and 42 may be separately tested, and both the output terminals SO1 and the input terminal SI2 need not be used at the same time.
In other words, when both the shift registers 41 and 42 are mounted on a single semiconductor chip, while the pads of the output terminal SO1 of the front-staged shift register 41 and the pads of the input terminal SI2 of the rear-staged shift register 42 are commonly used, these pads may be selectively used as pads of either terminal of either register.
Also, in the case that the switch circuit is provided between both the shift registers 41 and 42 so as to use these shift registers in the series manner, the input terminal SI2 of the rear-staged shift register 42 which is not used is required to be connected to either the power supply VDD or the ground potential VSS (namely, is fixed to either HIGH or LOW) in order to prevent floating (occurrence of penetration current). Then, when the pads of the output terminal SO1 and the pads of the input terminal SI2 are commonly used, these shift registers must be similarly arranged to prevent floating.
Also, as indicated in FIG. 11, the input terminal SI and the output terminal SO are connected via the buffer circuit 8 to the shift register 4. Normally, in the buffer circuit 8 connected so as to increase the output, plural stages of inverters and buffers are connected in a series manner as a gate group capable of gradually increasing the output. As a result, the electric power consumed in the respective stages is increased. In particular, when the switch circuit is provided between the shift registers 41 and 42 so as to use these shift registers in the series manner, the buffer circuit 8 connected to the output terminals SO1 and SI2 which are not used consumes useless electric power.
Furthermore, the following circuit arrangement may be generally conceived when both the shift registers 41 and 42 having the same structures are mounted on a single semiconductor chip in view of an element arranging efficiency. That is, D-FFs are continuously arranged by adjoining both the shift registers to each other. As a result, in general, when the switch circuit for connecting/disconnecting both the shift registers 41 and 42 is further mounted on the semiconductor chip, this switch circuit may be arranged on the side of the edge portions of both the shift registers 41 and 42 which are continuously arranged. However, when the switch circuit is arranged at the edge portion, the wiring distance between the series-connected shift registers 41 and 42 becomes long, so that the data transfer speed between the shift registers 41 and 42 is delayed.
Also, when the output terminal SO1 and the input terminal SI2 are also arranged at the edge portion in connection with the arranging position of the switch circuit at the edge portion, the wiring length of the input terminal SI2 of the rear-stages shift register 42 becomes longer than the wiring length of the input terminal SI1 of the front-staged shift register 41. Thus, there are some possibilities that the signal timing such as the set-up time xe2x80x9cstuxe2x80x9d and the hold time xe2x80x9cthexe2x80x9d may differ, depending upon both the shift registers.
To solve the above-explained problems of the prior art, the following means are employed. That is to say, a thermal head driving integrated circuit, according to the present invention, is basically to control energizing of a heating resistive elements in response to a data signal. This thermal head driving integrated circuit is provided with a driver in which at least two stages of shift registers are series-arranged in front and rear stages, the two-staged shift registers sequentially transfer data signals supplied thereto in a serial signal manner to store thereinto the transferred data signals, and the stored data signals are read out in a batch mode so as to drive a plurality of heating resistive elements. This thermal head driving integrated circuit employs switch means interposed between an input terminal and output terminal of the data signal with respect to the front-staged shift register, interposed between an input terminal and output terminal of the data signal with respect to the rear-staged shift register, and interposed between the output terminal of the front-staged shift register and the input terminal of the rear-staged shift register. As a featured aspect, the switch means selectively connect and disconnect the front-staged shift register and the rear-staged shift register series-connected to and from each other.
Preferably, the shift registers, the driver, and the switch means are formed on a semiconductor chip having an elongated shape in an integrated circuit form. In this case, the output terminals of driver side thereof, which are connected to the externally provided respective heating resistive elements are arranged along one long edge side of the semiconductor chip. Also, the input terminal of the data signal, the output terminal thereof, a power supply terminal, and a ground terminal, and also other control terminals are arranged along the other long edge side of the semiconductor chip. Preferably, the output terminals of the driver side are arranged in a staggered manner. Alternatively, the ground terminals are arranged in an array shape along a center of the semiconductor chip.
In such a case that a relatively high-speed printing operation is required, the front-staged shift register is separated or disconnected from the rear-staged shift register by way of the above-explained switch means, and the data signal is entered into the front-staged shift register and the rear-staged shift register at the same time. As a result, the transfer efficiency of the data signal is improved. On the other hand, when a relatively slow-speed printing operation is sufficient, the front-staged shift register and the rear-staged shift register are connected in series by employing the switch means. As a result, the input series of the data signals can be reduced by xc2xd, in view of the overall thermal head. In addition, since the switch means internally connects the front-staged shift register and the rear-staged shift register with each other, this switch means can suppress the stray capacitance which may give the adverse influence to the data transfer speed, and furthermore, can reduce the total number of processing steps required for the wire bonding work of the prior art.
Also, a thermal head driving integrated circuit, according to the present invention, is to control energizing of a heating resistive element in response to a data signal. The thermal head driving integrated circuit is provided with a driver in which at least two stages of shift registers are series-arranged in front and rear stages, the two-staged shift registers sequentially transfer data signals supplied thereto in a serial signal manner to store thereinto the transferred data signals, and the stored data signals are read out in a batch mode so as to drive a plurality of heating resistive elements. Then, the thermal head driving integrated circuit is equipped with an input terminal of the data signal with respect to the front-staged shift register, an output terminal of the data signal with respect to the rear-staged shift register, and switch means interposed between an output unit of the front-staged shift register and an input unit of the rear-staged shift register, for selectively connecting and disconnecting the shift registers series-arranged in the front and rear stages to and from each other. Furthermore, this thermal head driving integrated circuit is provided with a common terminal into or from which the data signal is inputted or outputted, and selecting means for selectively connecting the common terminal with any one of the output unit of the front-staged shift register and the input unit of the rear-staged shift register.
Preferably, the switch means and the selecting means are mutually operated in conjunction with each other, and in the case that the switch means connects the front-staged shift register and the rear-staged shift register in series, the selecting means connects the output unit of the front-staged shift register to the common terminal. Preferably, the switch means and the selecting means are arranged by either a tri-state buffer or a tri-state inverter.
In accordance with the present invention, the output terminal of the front-staged shift register and the input terminal of the rear-staged shift register are not separately provided, but one common terminal is switched by the switch means so as to be commonly used. As a result, the total number of terminals can be reduced. The semiconductor chip can be made compact. Also, since the total number of bondings is reduced, the quality can be improved.
Also, a thermal head driving integrated circuit, according to the present invention, is to control energizing of a heating resistive element in response to a data signal. The thermal head driving integrated circuit is provided with one stage, or two stages of shift registers series-arranged in front and rear stages, for sequentially transferring data signals supplied thereto in a serial signal manner to store thereinto the transferred data signals; a driver for reading out the data signals stored in the shift registers in a batch mode so as to drive a plurality of heating resistive elements; and also an input terminal and output terminal of the data signal with respect to each stage of the shift registers. As a featured aspect, this thermal head driving integrated circuit is provided with connecting/disconnecting means for disconnecting a buffer circuit from a power supply, the buffer circuit being connected to a terminal which is not used in some cases out of the input terminal and the output terminal. Preferably, the connecting/disconnecting means is arranged by either a tri-state buffer or a tri-state inverter.
In accordance with the present invention, since the buffer circuit can be disconnected from the buffer circuit and this buffer circuit is connected to such an unused terminal as the output terminal of the front-staged shift register and also the input terminal of the rear-staged shift register in the case that, for example, two stages of shift registers are series-connected, the power consumption of this buffer circuit can be suppressed while this buffer circuit is not used.
Also, the thermal head driving integrated circuit, according to the present invention, includes either the switch means or the switch means and the selecting means which are arranged between the front-staged shift register and the rear-staged shift register.
Since the switch means is arranged between both the shift registers, the wiring distance when both the shift registers are series-connected can be shortened, it is possible to avoid a delay occurred in the data transfer speed between these shift registers.
Since the switch means is arranged at an intermediate portion between both the shift registers, the input terminal of the rear-staged shift register can be positioned in the vicinity of the rear-staged shift register, and the wiring distances of both the input terminals of the shift registers can be made substantially equal to each other. Also, since the selecting means is also arranged between both the shift registers, the wiring distances of both the input terminals of the shift registers can be made substantially equal to each other. Also, since the wiring distances of the input terminals can be made substantially equal to each other, the signal timing can be made equal to each other, so that the characteristic of the thermal head with respect to the high speed printing operation can be improved.